Generally, various advanced processes may be utilized in the design and fabrication of IC devices, particularly to aid with forming multi Vt channels in an IC device. Current processes, for example, utilizing lanthanum-oxide (La2O3) and channel doping in 10 nm node devices, may cause performance degradation and be unsuitable in smaller technology nodes. Such processes may include higher thermal ranges as well as a chemical reaction to achieve uniform Vt shift in short and long channels in an IC device. A plasma channel doping process may be inconsistent due to plasma life time difference in short and long channels. Additionally, different work-function (WF) materials are utilized in different device types (e.g. n-type or p-type) that may require additional lithography steps.
Therefore, a need exists for a methodology enabling formation of multi Vt channels in an IC device, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices.